A semiconductor device including a PLL circuit having a built-in VCO, a plurality of frequency dividing circuits, and a selection circuit is known (refer to Patent Document 1). The plurality of frequency dividing circuits output a plurality of 1/N-frequency division clock signals based on the output frequency of the PLL circuit, and one of them can output a frequency division output after the decimal point. The selection circuit selects one of the frequency division outputs outputted from the plurality of frequency dividing circuits by mode setting, and outputs the clock signal of a selected frequency division ratio.
Besides, a clock generating circuit that frequency-divides an input clock based on frequency division ratio data is known (refer to Patent Document 2). The clock generating circuit includes a frequency division ratio identifier that identifies the frequency division ratio data as an even number, an odd number, or a decimal number, and also includes a delay device and a frequency divider. The delay device includes the number (M), corresponding to M=9×p+(p−1), of delay taps so as to change the delay amount in multiple stages, while including a tap selection unit that controls the delay amount by selecting at least one of the plurality of delay taps. Note that p represents the number of digits after decimal point in the frequency division ratio data composed of a decimal number. When the frequency division ratio identifier identifies the frequency division ratio data as a decimal number, the delay device delays the input clock to generate a delay clock, and the frequency divider frequency-divides the input clock using a rise and a fall of the edge of the delay clock and using a rise and a fall of the edge of the input clock.
[Patent Document 1] Japanese Laid-open Patent Publication No. 2004-056717
[Patent Document 2] Japanese Laid-open Patent Publication No. 2006-268617
However, Patent Document 1 is for generating a divide-by-1.5 divided output signal based on four-phase clocks.